SK Hynix Develops Compute Express Link (CXL) memory modules
The head of SK Hynix’s parent group told Bloomberg TV that the company may move beyond selling memory chips and offer “Memory as a Service” (MaaS) — memory capacity delivered like a cloud subscription rather than a product shipped in a box.
He was candid that MaaS is still “an idea at this point.” No pricing, no timeline. But the concept itself is not new, and the hardware that would make it possible has been taking shape for several years. Most IT buyers just haven’t had a reason to follow it.
Here is what Memory as a Service actually means, why memory makers want it, and the technology that would carry it.
The problem: RAM is stranded inside servers
In a traditional data center, every stick of RAM is captive to one machine. A database server maxing out its 512 GB cannot borrow a single gigabyte from the idle box in the next rack slot. The DIMMs are physically removable, but during operation they are logically bound to one machine and no other.
The result is chronic over-provisioning. Operators size each server for its worst-case workload, then watch most of that capacity sit underused most of the time. Industry engineers call this stranded memory, and AI has turned it from an accounting annoyance into a real constraint.
Large Language Model inference is the clearest example. The working memory an LLM builds up during a conversation — the KV cache — can easily exceed 80 to 120 GB per GPU, depending on model size, context length, and batch count. When it overflows, data spills to storage over the network, and performance degrades sharply.
What “as a service” means for memory
MaaS applies the cloud playbook to DRAM. Instead of buying memory and bolting it into individual servers, an operator draws capacity from a large shared pool, paying for what gets used. In SK’s telling, the supplier would provide memory configurations and software together, tuned to a customer’s AI models — closer to how Amazon or Google lease compute than how a chip vendor ships DIMMs today.
For that to work, memory first has to escape the server chassis. That is a hardware problem, and it has a name: disaggregation.
The enabler: CXL
Pulling RAM out of a server was long considered a dead end. Memory is latency-sensitive in a way storage is not, and anything hanging off a standard PCIe slot was simply too slow to treat as main memory.
Compute Express Link (CXL) changed the math. It is an open standard that runs over PCIe’s physical wiring but adds the piece PCIe never had: cache coherency, meaning the CPU, GPU, and external memory all agree on the current state of shared data. Its CXL.mem sub-protocol lets a processor issue ordinary load and store instructions against memory sitting outside the box, as if it were on the motherboard.
The honest caveat: external CXL memory is not as fast as local DRAM. In published measurements, access latency lands in the 200 to 500 nanosecond range — a few times slower than a local DIMM, comparable to reaching memory attached to another CPU socket. Real deployments will vary; every switch hop and fabric layer adds time.
But compare the alternatives. NVMe storage sits around 100 microseconds, hundreds of times slower. For workloads that would otherwise spill to disk or shuffle data across a network, CXL memory is dramatically faster than the fallback, even if it never beats the DIMM next to the CPU.
The standard has matured in steps: CXL 1.0 established coherent host-to-device links, 2.0 added switching and memory pooling, and 3.0 introduced fabric topologies and multi-level switching that make coherent sharing across many hosts possible. Whether a given rack actually shares memory that way is a design choice, not something the spec hands out for free.
The building blocks: memory appliances and CXL switches
A disaggregated rack replaces some traditional servers with two new kinds of hardware.
Memory appliances are chassis dedicated almost entirely to DRAM. The industry nickname — “just a bunch of memory” — deliberately echoes the “just a bunch of disks” shelves familiar from storage. They attach to the rack fabric and exist purely to serve capacity to other machines.
CXL switches are the traffic directors. Marvell’s Structera S 30260, announced in March, is a 260-lane CXL 3.0 switch with up to 4 TB/s of aggregate bandwidth, built to let CPUs, GPUs, and other accelerators dynamically claim slices of a rack-level memory pool. It is expected to sample to customers in the third quarter of 2026, which says something about where this market sits: real silicon, early days.
In demonstrations, the pooled approach has shown meaningful gains for LLM inference — a 3.8x speedup over 200G RDMA networking in one two-server test, with pool capacity scalable to 100 TiB per cluster.
None of this is a one-company project, either. The CXL Consortium’s membership spans essentially every major CPU, GPU, and memory vendor — Intel, AMD, Samsung, Micron, and SK Hynix included — and current server processors from both Intel and AMD already speak the protocol. Samsung and Micron sell CXL expansion modules today, and controller makers such as Astera Labs and Marvell ship the silicon in between. SK may be the first to float a subscription label, but the plumbing underneath is an industry-wide effort.
Tiering: local DRAM still comes first
Because pooled memory is slower than local memory, disaggregated systems treat them as tiers. Hot data — the values a processor is actively computing on — stays in local DRAM or HBM. Warm data that is too big for local memory but too active for storage, like a large KV cache or an in-memory database’s buffer pool, lives in the CXL pool. Hardware and OS-level monitoring migrate data between tiers as access patterns shift.
Anyone who remembers the tradeoffs of NUMA systems (Non-Uniform Memory Access), where memory attached to a distant CPU socket costs extra cycles, will recognize the pattern. The industry has managed uneven memory speeds for decades. CXL extends that discipline from the motherboard to the rack.
The less glamorous half of the problem is software. Tiered and pooled memory only pays off when the operating system knows which pages are hot, migrates them without stalling applications, and exposes the pool to hypervisors and schedulers in a form orchestration layers can actually use. Meta paired its hardware with a page-placement software layer that decides per workload how much slower memory each application can tolerate — and switches it off entirely for workloads that can’t. Any vendor renting memory as a service will have to solve those problems for customers’ kernels, hypervisors, and Kubernetes clusters, not just their racks.
Not theoretical: Meta already deploys CXL memory expansion at scale
Skepticism toward new interconnect standards is healthy — plenty have died on the whiteboard. CXL has cleared that bar.
Meta recently disclosed a custom CXL 2.0 controller chip, called Vistara, that lets DDR4 modules pulled from decommissioned servers plug into new DDR5-only platforms as a second memory tier. Each of its memory servers pairs 768 GB of local DDR5-6400 with 256 GB of CXL-attached DDR4-2400. The logic is simple: servers retire after three to five years, but the DIMMs inside them are good for seven to ten.
Meta reports roughly 25% fewer servers needed for its disaggregated AI inference workloads and a third fewer out-of-memory failures, deployed across a fleet of millions. Those figures are specific to Meta’s workloads and won’t transfer one-to-one anywhere else — but they are production numbers, not lab projections.
Worth noting the distinction. Meta’s setup is memory expansion — adding a slower tier inside a single server, no switch involved. Rack-level pooling, the architecture MaaS depends on, needs the CXL 3.0 switching described above. Expansion is the production-proven first step; pooling is the next one.
Why a memory maker wants subscriptions
The technical story explains how MaaS could work. The business story explains why SK is floating it.
Memory manufacturing is famously cyclical: gluts crash prices, shortages spike them, and producers swing between record profits and deep losses. The current AI build-out is a spike — one forecast circulating in the trade press puts the cumulative rise in combined DRAM and SSD prices at as much as 130% by the end of 2026. That is an upper-bound projection, not a settled figure, but the direction is not in dispute. Selling capacity as a subscription would smooth that revenue into something recurring and predictable, the same reason software vendors abandoned perpetual licenses.
It would also dovetail with SK Group’s plan to invest roughly $1 trillion over ten years in AI data centers, securing 15 gigawatts of capacity in Korea and 5 more overseas. A company that operates data centers and makes the memory inside them is well positioned to rent that memory out.
Whether customers want their DRAM on subscription is a separate question. Operators have resisted vendor lock-in in every other “as a service” wave, and memory would be no different.
What this means for hardware that already exists
Disaggregation is a forward-looking architecture, but it has a present-day implication: the industry is getting better at treating memory as an asset with value independent of the server it shipped in. Meta’s DDR4 reuse makes the point at hyperscale — the clearest signal yet of second-life demand for older memory — and the same logic applies to everyone else’s decommissioned hardware.
Servers pulled from racks today are full of DDR4 and DDR5 modules that carry real market value — especially now, with DRAM prices elevated. And the DIMMs are not the only parts that outlive their chassis: the same retired machines give up server CPUs and GPUs with years of useful life left in them.
Businesses retiring equipment can sell that memory and those components rather than letting them depreciate in a storage closet, which is the small-scale version of the same principle CXL pooling applies at rack scale: stop stranding RAM.
MaaS itself remains an idea, not a product line. But the pieces — the protocol, the switches, the appliances, and now a major manufacturer’s stated interest — are lining up. The next signal to watch is whether SK attaches a price sheet to the concept, and whether the first CXL 3.0 switches reach customers for sampling this quarter as planned.